Chisel assigning to individual bits of UInt

Question

Can someone enlighten me as to why the following code will not elaborate in Chisel? It appears I am not able to assign to individual bits in a UInt. Is this by design?

I did see Jack's response to a similar question, but the following type of logic across bits of a strand is common and easily parameterized in SV, etc. I can see creating a Vector of Bools as well as the individual bits, but still the problem of how to get back into a UInt...

  def ffo(pwidth:Int, in:UInt) : UInt = {
    val rval = Wire(UInt(width=pwidth))
    rval(0) := in(0)
    for(w <- 1 until pwidth) {
      rval(w) := in(w) & !( in(w-1,0).orR() )
    }
    rval
  }

Results in:

firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 21:13:@5808.4]: [module IuIrRename]  Expression T_1824 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 23:15:@5815.4]: [module IuIrRename]  Expression T_1826 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 23:15:@5822.4]: [module IuIrRename]  Expression T_1834 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 23:15:@5829.4]: [module IuIrRename]  Expression T_1842 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 21:13:@5834.4]: [module IuIrRename]  Expression T_1851 is used as a FEMALE but can only be used as a MALE.

Answer 1

After continuing experiments (and after looking at the generated Verilog) the following code is equivalent to what I was looking for:

  def ffo(pwidth:Int, in:UInt) : UInt = {
    val ary = Wire(Vec(pwidth, Bool()))
    ary(0) := in(0)
    for(w <- 1 until pwidth) {
      ary(w) :=   in(w) && !( in(w-1,0).orR() )
    }
    val rval = Reverse(Cat(ary))
    rval
  }