Chisel 3 assignment to bit range

Question

This seemed to work in Chisel 2, but doesn't work now:

class TestX extends Module
{
    val io = IO(new Bundle {
        val a = Output(UInt(width=2))
    })

    io.a(1, 0) := UInt(0)
}

Error: [module TestX] Expression T_4 is used as a FEMALE but can only be used as a MALE.

What's the fix for this change?

Answer 1

Chisel3 does not currently support subword assignment. That error message is pretty unhelpful though, I've filed an issue: https://github.com/ucb-bar/chisel3/issues/399.

You can solve this problem by using extraction and concatenation:

class TestX extends Module {
  val io = IO(new Bundle {
    val a = Input(UInt(4.W))
    val b = Output(UInt(4.W))
  })
  io.b := Cat(io.a(3, 2), 0.U(2.W))  
}

EDIT: Updated with modern syntax