Can I use Preprocessor Directives in .ld file

Question

Can I use Preprocessor Directives in .ld file? I need to to use one of two sets of .ld file and wants to let Build engine deside that using macro, Can I do that?

Answer 1

Yes, you can. You need to run preprocessor manually for your linker script, like this:

in="your_linker_script.ld"
out="generated_script.ld"
cflags=-Iinclude/

gcc -E -x c $cflags $in | grep -v '^#' >$out

Flags:

• -E specifies GCC to only run preprocessor
• -x c tells GCC to treat your linker script as C source file (it's needed to run GCC with your LD script)

Or you can simply use cpp tool, which is actually C preprocessor.

After this you will be able to use generated linker script to build your program (e.g. in Makefile).

Example

Here is how I solved this problem in my project:

1. Here is my linker script uses preprocessor (#include directive and CONFIG_TEXT_BASE constant). Excerpt:

    #include <config.h>
   
    . = CONFIG_TEXT_BASE;
   

2. Here is script to generate preprocessed linker script. Excerpt:

    gcc -E -x c -Iinclude $cflags $in | grep -v '^#'    >>$out
   

3. Here is my Makefile, it's generating preprocessed linker script at $(LDS_GEN) target (line 53) and the this generated script is being used to build result binary (line 42). Excerpt:

    $(LDS_GEN): $(LDS)
            build/gen-lds.sh $(LDS) $(LDS_GEN) $(CFLAGS)
   
    $(APP).bin: $(OBJS) $(LDS_GEN)
            $(LD) $(OBJS) -T $(LDS_GEN) -o $(APP).elf