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target: TargetA ../DirB/FileB.cpp ../DirC/FileC.o ../DirD/FileD.o ...
This is a long line in a make file. Is it possible to break this into several lines?
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As in normal makefile syntax, a single logical recipe line can be split into multiple physical lines in the makefile by placing a backslash before each newline. A sequence of lines like this is considered a single recipe line, and one instance of the shell will be invoked to run it.
Show activity on this post. Then make , make target1 , make target2 , and so on will all do what you want. You say your makefile "derives the SRC list from [ $(TARGET) ]" in some presumably high-tech way, but it might be interesting to try explicitly listing the object files in a low-tech way instead, as above.
The $@ and $< are called automatic variables. The variable $@ represents the name of the target and $< represents the first prerequisite required to create the output file.
' # ' in a line of a makefile starts a comment. It and the rest of the line are ignored, except that a trailing backslash not escaped by another backslash will continue the comment across multiple lines.
from the documentation https://www.gnu.org/software/make/manual/make.html#Splitting-Lines
Makefiles use a “line-based” syntax in which the newline character is special and marks the end of a statement. GNU make has no limit on the length of a statement line, up to the amount of memory in your computer.
However, it is difficult to read lines which are too long to display without wrapping or scrolling. So, you can format your makefiles for readability by adding newlines into the middle of a statement: you do this by escaping the internal newlines with a backslash (\) character.
It works for targets too, i.e.:
a b c d: touch $@ multiline_dependencies: a \ b \ c \ d touch $@ and to verify, make multiline_dependencies --dry-run gives the following output
touch a touch b touch c touch d touch multiline_dependencies There are a couple ways of doing this. One simple way:
target: targetA targetB target: targetC targetD target: @echo $@ is dependent on $? Note that this will not work with pattern rules through (rules with % in the targets/dependencies). If you are using pattern rules (and even if you're not), you can consider doing something like:
TARGET_DEPS := targetA targetB TARGET_DEPS += targetC TARGET_DEPS += targetD target: $(TARGET_DEPS) @echo $@ is dependent on $? While it's possible to use the backslash, I personally find this makes the makefiles harder to read as the meaning of the indentation becomes unclear.
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