Allow space in target of GCC makefile

Question

Is there a way to get spaces inside target names working when using make.exe? It seems to be impossible if this really ancient bug report is correct: http://savannah.gnu.org/bugs/?712

For reference, the big problem is that pieces of makefile commands like:

"foo bar baz": $(OBJ)
    $(CPP) $(LINKOBJ) -o $(BIN) $(LIBS)

... seem to get treated as three separate commands: one to build "foo (note the included "), one to build bar, and lastly, one to build baz" (again, including "). This is because make.exe seems to be using space as a delimiter.

However, it's reasonable to assume that one might want to build "Hello World.exe" for example. This doesn't seem to be possible. Double quotes don't work, and neither does escaping the separate words (I've read that somewhere, don't remember the link):

"foo\\ bar\\ baz": $(OBJ)
    $(CPP) $(LINKOBJ) -o $(BIN) $(LIBS)

Is there any other way to fix this? The official manual only confirms the tokenize-by-spaces stuff, but doesn't provide a way to use space for any other purpose: http://www.gnu.org/software/make/manual/make.html#Rule-Syntax

Edit: as suggested, I've tried single slashes too, but these have the exact same effect as double slashes. Make complains it can't find rules for the first word:

mingw32-make.exe: *** No rule to make target `foo', needed by `all'.  Stop.

The executable "foo bar baz.exe" is correctly produced though, but linking is done each time per word.

Answer 1

Instead of double backslash use single ones. The following Makefile works (at least for gnu make):

goal:   foo\ bar

foo\ bar:
    gcc -o "foo bar" "foo bar.c"