ADDRESS WIDTH from RAM DEPTH

Question

I am implementing a configurable DPRAM where RAM DEPTH is the parameter.

How to determine ADDRESS WIDTH from RAM DEPTH?

I know the relation RAM DEPTH = 2 ^ (ADDRESS WIDTH)

i.e ADDRESS WIDTH = log (base 2) RAM DEPTH.

How to implement the log (base 2) function in Verilog?

Answer 1

The $clog2 system task was added to the SystemVerilog extension to Verilog (IEEE Std 1800-2005). This returns an integer which has the value of the ceiling of the log base 2. The DEPTH need not be a power of 2.

module tb;  parameter DEPTH = 5; parameter WIDTH = $clog2(DEPTH);  initial begin     $display("d=%0d, w=%0d", DEPTH, WIDTH);     #5 $finish; end  endmodule 

Running a simulation will display this:

d=5, w=3 

However, I do not know of a synthesis tool which supports $clog2. If you need to synthesize your code, you can use a function. This was copied from the IEEE 1364-2001 Std, but there are other versions floating around the web:

function integer clogb2;     input [31:0] value;     begin         value = value - 1;         for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin             value = value >> 1;         end     end endfunction 

My experience has been that using the function is more trouble than it's worth for synthesizable code. It has caused problems for other tools in the design flow (linters, equivalence checkers, etc.).