Active-HDL simulation clock crossing

Question

I have 2 modules using the same clock but in different files, when I sample signal that come from module A in module B , in the Waveform simulation it doesn't get samples after one clock cycle like it should , it shows that is samples in the same rising edge(behavior that fit to asynchronous instasiation) .

I have been told it happens because Active-HDL consider it to 2 differnet clock because of the different component and thats why it sample in the same rising edge(because of the delta time that the signal goes from A to B).

how can i define that Active-HDL will understand they both use the same clock in same area ?

Answer 1

This has nothing to do with your simulator. I assume that you're doing something like this:

        +----------+           +----------+
        |          |-- clk --->|          |
clk --->| Module A |           | Module B |
        |          |-- data -->|          |
        +----------+           +----------+

where you should be doing something like that:

        +----------+           +----------+
        |          |           |          |
clk -+->| Module A |-- data -->| Module B |
     |  |          |           |          |
     |  +----------+           |          | 
     |                         |          |
     +-----------------------> |          |
                               +----------+

The problem with the first configuration is that your clock signal gets delayed by one or more delta cycles when it goes through module A. It may thus toggle in the same, or in a later delta cycle than the data signal. This is something that you will not see in the simulator's waveform view (unless it has an option to expand delta cycles) but you can have a look at the list view to see exactly what happens in delta-time.