what is the difference between -> and => in system verilog assertions?

Question

I wanted to know when to use -> and => in SVA. Are there any differences between:

sequence A;
 req |-> ##1 gnt;
endsequence

and:

sequence B;
 req |=> ##1 gnt;
endsequence

Please let me know.

Answer 1

|=> is equivalent to |-> ##1
Therefore, req |=> ##1 gnt; is equivalent to req |-> ##2 gnt;

Refer to IEEE Std 1800-2012 § 16.12.6 Implication