What does |variable mean in verilog?

Question

I am wondering what assign hd_trs_detected = |hd_trs_match; means in verilog. I am mostly interested in the |hd_trs_match part. I know that | means bit wise OR, but not sure how to interpret it without a value before the |. Is it an understood '1' or '0'? If it is a '0', what would be the advantage of using |hd_trs_match vs. just hd_trs_match as hd_trs_detected would always be whatever hd_trs_match is? Or could it be a bit wise operation of itself.

Answer 1

The | is a reduction operator. For a multi-bit signal, it produces an output applying the operand to each bit of the vector.

For example,

wire [3:0] in;
wire out;
assign out = |in; // the same as out = in[3] | in[2] | in[1] | in[0];

You can do the same with &, ^, etc.