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New posts in simd

AVX2, How to Efficiently Load Four Integers to Even Indices of a 256 Bit Register and Copy to Odd Indices?

x86 sse simd avx avx2

Why are SIMD instructions not used in kernel?

linux-kernel operating-system linux-device-driver simd ispc

How to convert 32-bit float to 8-bit signed char? (4:1 packing of int32 to int8 __m256i)

c x86 simd intrinsics avx2

Summing 3 lanes in a NEON float32x4_t

ios arm simd neon intrinsics

What is the difference between MOVDQA and MOVNTDQA, and VMOVDQA and VMOVNTDQ for WB/WC marked region?

assembly x86 sse simd avx

AVX2 VPSHUFB emulation in AVX

x86 simd intrinsics avx

_mm_alignr_epi8 (PALIGNR) equivalent in AVX2

x86 simd intrinsics avx avx2

How do you move 128-bit values between XMM registers?

assembly simd sse

Setting __m256i to the value of two __m128i values

c sse simd avx

Loading 8 chars from memory into an __m256 variable as packed single precision floats

c++ sse simd avx avx2

Shuffling by mask with Intel AVX

c++ sse simd intrinsics avx

Control flow divergence in SIMT and SIMD

cuda sse simd

Are there SIMD(SSE / AVX) instructions in the x86-compatible accelerators Intel Xeon Phi?

intel sse simd avx intel-mic

Faster lookup tables using AVX2

algorithm performance optimization sse simd

Does using mix of pxor and xorps affect performance?

assembly x86 sse simd

Is there an efficient way to get the first non-zero element in an SIMD register using SIMD intrinsics?

x86 bit-manipulation simd intrinsics avx

Using a variable to index a simd vector with _mm256_extract_epi32() intrinsic

simd intrinsics avx avx2

Is casting to simd-type undefined behaviour in C++? [duplicate]

c++ sse undefined-behavior simd intrinsics

What's the most efficient way to load and extract 32 bit integer values from a 128 bit SSE vector?

c gcc sse simd

ARM and NEON can work in parallel?

arm inline-assembly simd neon cortex-a8
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