I am a newbie to modelsim and Verilog. I designed a DFF(D flip flop module) and a test bench for testing it. But I can't get why modelsim give me this error:
No objects found matching '/test/*'
test bench code:
// Testbench
module test;
reg clk;
reg reset;
reg d;
wire q;
wire qb;
// Instantiate design under test
dff DFF(.clk(clk), .reset(reset),
.d(d), .q(q), .qb(qb));
initial begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1);
$display("Reset flop.");
clk = 0;
reset = 1;
d = 1'bx;
display;
$display("Release reset.");
d = 1;
reset = 0;
display;
$display("Toggle clk.");
clk = 1;
display;
end
task display;
#1 $display("d:%0h, q:%0h, qb:%0h",
d, q, qb);
endtask
endmoudle
DFF code:
// Design
// D flip-flop
module dff (clk, reset,
d, q, qb);
input clk;
input reset;
input d;
output q;
output qb;
reg q;
assign qb = ~q;
always @(posedge clk or posedge reset)
begin
if (reset) begin
// Asynchronous reset when reset goes high
q <= 1'b0;
end else begin
// Assign D to Q on positive clock edge
q <= d;
end
end
endmodule
for simulating I first compile both files then simulate the test bench. after this, I go to the wave windows and try to put the test into the wave but at this point I get the error I have mentioned at the first.
The problem was with the optimization. I simulate this code with:
vsim -novopt destination
and everything went fine.
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