Avoiding race conditions without using program blocks in systemverilog

Question

We know that program blocks are used in SystemVerilog to avoid race conditions between DUT and testbench. What did the verification engineers do before SystemVerilog came into picture? I can only think of using hand shake signals.

Answer 1

You use the same semantics that designers use to prevent race conditions in RTL: Non-blocking assignments, or alternative clock edges.

Program blocks are an unnecessary construct in SystemVerilog. See http://go.mentor.com/programblocks

Answer 2

You can avoid race condition without using program block.

Race condition is created just because of expression or assignments are try to access same signal at a same time.

If two signals try to access same signal at different time stamp then user can remove race condition.

Actually code is written in verilog or system verilog is execute in different time region like active region, reactive region.

Race condition can be removed using following things.

(1) Program block

(2) Clocking block

(3) Non blocking assigment

Before program block and clocking block race condition is removed using non blocking assignment.

As I explained above statement written in verilog code or system verilog code is not execute code in single time same. There are different region in which specific syntax is executed by tool.

Here I mainly talked about Active and Reactive region. Active region consider continuous assignments, blocking assignments. Reactive region consider LHS of non blocking assignments are evaluated in this region.

First active region is evaluated then reactive region is evaluated.

So before program block to remove race condition verification engineers take care of this things(regions of execution).

Now in system verilog there are many other regions are added like prepone region, observed region, postpone region.