Align code in Emacs Verilog Mode?

Question

I'm used to writing code in VHDL in emacs, which has the nice beautify functionality that will align signal assignments. Is there something similar with the Verilog Mode?

Convert this:

r_Tx_Done <= 1'b1;
r_Clock_Count <= 0;
if (r_Done == 1'b1)
  begin
    r_SM_Main <= s_CLEANUP;
    o_Tx_Active <= 1'b0;
  end

To This:

r_Tx_Done     <= 1'b1;
r_Clock_Count <= 0;
if (r_Done == 1'b1)
  begin
    r_SM_Main   <= s_CLEANUP;
    o_Tx_Active <= 1'b0;
  end

Verilog mode does a good job keeping if else begin end aligned, but it doesn't align assignments like I want. Note that inside the if statement doesn't align to <= outside the if statement. Essentially I want each begin/end block treated separately.

Answer 1

I use verilog mode, and I have found this works by default.

1. Type C-x h to highlight the entire buffer.
2. Then TAB to get it to beautify everything. Much easier and less tedious!