Which mode does the SVC handler start in?

Question

Which mode does the ARM SVC handler start in? Basically, I want to know which mode the ARM core is in when an SVC exception is raised?

Can't seem to find it in the ARM ARM, but my guess would be that it starts in Supervisor.

Answer 1

Are you talking about the SWI handler? Yes, I see some places they refer to it as the SWI instruction but sometimes the SVC instruction.

Note: In older versions of the ARM architecture, SVC was called SWI, Software Interrupt.

From the ARM ARM

Exception type           Mode       Address
----------------------------------------------
Reset                    Supervisor 0x00000000
Undefined Instruction    Undefined  0x00000004
Software Interrupt (SWI) Supervisor 0x00000008
Prefetch Abort           Abort      0x0000000C
Data Abort               Abort      0x00000010
IRQ                      IRQ        0x00000018
FIQ                      FIQ        0x0000001C

...

Software Interrupt exception

The Software Interrupt instruction (SWI) enters Supervisor mode to request a particular supervisor (operating system) function. When a SWI is executed, the following actions are performed:

R14_svc = address of next instruction after the SWI instruction
SPSR_svc = CPSR
CPSR[4:0] = 0b10011  /* Enter Supervisor mode */
CPSR[5] = 0          /* Execute in ARM state */
                     /* CPSR[6] is unchanged */
CPSR[7]= 1           /* Disable normal interrupts */
                     /* CPSR[8] is unchanged */
CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */
PC = 0x00000008

To return after performing the SWI operation, use the following instruction to restore the PC (from R14_svc) and CPSR (from SPSR_svc) and return to the instruction following the SWI: MOVS PC,R14