what is the difference between slice registers and slice LUTs in Xilinx FPGA?

Question

What is the difference between "slice registers" and "slice LUTs" in Xilinx FPGA?

Why is the number of slice registers equal to the number of slice LUTs in Vertix 5 for example, but the number of slice registers is double the number of slice LUTs in both Vertix 6 and Vertix 7?

Answer 1

LUT (Look-Up Table) is a small asynchronous SRAM that is used to implement combinational logic, while FF (Flip-Flop) is a single-bit memory cell used to hold state.

LUTs are usually read-only and their content can only be changed during FPGA configuration. But in Xilinx FPGAs afaik usually half of LUTs can actually be written to, so they can be used to implement many small RAMs (so-called "distributed RAM"). Flip-flops can be written to and in fact, it is their main purpose.

Flip-flop value can be accessed directly and can be routed to any place you want, while reading LUT content requires an address, so you can only access a single stored bit at a time. Because of this LUTs can store more than flip-flops.

why is the number of slice registers is equal to the number of slice LUTs in vertix 5 for example, but the number of slice registers is double the number of slice LUTs in both vertix 6 and vertix 7?

They just decided to increase number of flip-flops on FPGA, so they put twice as many in each slice. Adding more LUTs was either too expensive or considered not very useful. FPGA has to have enough of both for your design to fit in there, having more elements of one type is meaningless if your design needs others.