What does it mean for a Makefile to "relink"? [closed]

Question

Can someone explain in simple terms:

1. What does it mean for a Makefile to relink ?
2. Why does it happen?
3. How to avoid it?

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Answer 1

A primary feature of make is that dependencies are specified in a makefile (often named makefile but may have other names such as MyRules.mk) in a form like:

FileX: FileA FileB FileC
    Command to make FileX from FileA FileB FileC

Given this dependency, if any of FileA, FileB, or FileC has a modification time later than the modification time of FileX, then make will execute the command to make a new version of FileX.

A common dependency rule says that an object file depends on a C source file and some header files, such as:

foo.o: foo.c foo.h project.h
    $(CC) -c foo.c

In makefiles for substantial projects, the rules and lists of files are often more complicated, using multiple symbols to convey commands, options, and lists of files.

Another common rule says to make an executable file out of object files:

MyProgram: foo.o bar.o baz.o
    $(LD) -o $@ $^

In this context, “relink” merely means that make will execute the command to link objects into an executable again. It happens either because one of the prerequisite files (an object file, often with a name ending in .o) is newer than the target executable file or because the rules in the makefile have not been written to properly express the dependencies.

Avoiding it is a matter of understanding how make and its rules and makefiles work.