VHDL - How to elegantly initialize an array of std_logic_vector?

Question

I'm trying to interface to a classic HD44780 LCD. I have implemented local ram to which I write the data I wish to show up on the display.

I have defined the ram in this way:

type ram_type is array (0 to (16*2)-1) of std_logic_vector(7 downto 0);
signal lcd_mem : ram_type;

I've tried initializing the ram in this way:

lcd_mem(0 to 6) <= x"45_72_72_6F_72_73_3A";
...

But I receive an error on synthesis:

Error (10515): VHDL type mismatch error at display_ber.vhd(74): ram_type type does not match string literal

Is there a way to ellegantly initialize the ram block in a similar way ?

Perhaps I should use a string type instead ?

Answer 1

Yes there is. Note that your definition of ram_type is an array of std_logic_vector. And x"45_72_72_6F_72_73_3A" is a hex string literal. These are not the same type, hence your error.

So, you have to put the value into an array of vectors. Such as:

lcd_mem(0 to 6) <= (0 => x"45", 1 => x"72", 2 => x"72", 3 => x"6F", 4 => x"72", 5 => x"73", 6 => x"3A");