VHDL alias syntax "<< ... >>"

Question

I'd like to understand the syntax used in the line of code below where an alternate name is created using an ALIAS declaration. Specifically, I'd like to know what the << and >> imply. An example alias statement is,

alias x2_dac_data is
   << signal server.x2_dac_data : std_logic_vector(23 downto 0) >>;

where server is an instantiated component and x2_dac_data is a signal with the component, but not listed in the port declaration.

I've reviewed Pedroni's text and a course guide, neither of which reference the << ... >> syntax as it relates to alias.

Thanks