Matthew Taylor

Matthew Taylor has asked 4 questions and find answers to 44 problems.

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Trainer for digital design, VHDL, Verilog, SystemVerilog and UVM.

Matthew Taylor questions

Is recursive instantiation possible in Verilog?

Matthew Taylor answers

What is the best practice to handle invalid or illegal combinations of inputs in a verilog module?
verilog bit shift with 1
Generate custom waveform in verilog
In VHDL, what does an unconstrained array's index range default to when passed as an argument to a function/procedure?
SystemVerilog: associative array of dynamic arrays
How can I write an alias in VHDL (post-87; i.e. 93, 2008) for a function call?
I'm getting this error for my verilog code, "Illegal operation for constant expression"
System Verilog- Wait statements
Increment enumeration type in VHDL
VHDL: This construct is only supported in VHDL 1076-2008