Alex

Questions Linux Laravel Mysql Ubuntu Git Menu

HTML CSS JAVASCRIPT SQL PYTHON PHP BOOTSTRAP JAVA JQUERY R React Kotlin

Alex has asked 129 questions and find answers to 12 problems.

Stats

About

Alex questions

If we marked memory as WC(Write Combined), then do we have any consistency automatically?
What difference between cudaDeviceScheduleBlockingSync and cudaDeviceScheduleYield?
Can I use in RDMA via Infiniband Load/Store access from GPU2-Cores to GPU1-RAM in the different PCIe-Bus?
What is the main difference between RSS, RPS and RFS?
Does the official OpenCL 2.2 standard support the WaveFront?
Do atomic CAS-operations on x86_64 and ARM always use std::memory_order_seq_cst?
What is the difference between cudaMemcpy() and cudaMemcpyPeer() for P2P-copy?
Is there any sense to use autoencoder for network with batch normalization?
Are GPU Kepler CC3.0 processors not only pipelined architecture, but also superscalar? [closed]
What is the maximum length of the cable can be for infiniband(RDMA)?

Alex answers

should I label and train on all objects that exist in the training set (yolo darknet)
Concatenating template parameter packs for a unary argument
Does the semantics of `std::memory_order_acquire` requires processor instructions on x86/x86_64?
Does atomic_thread_fence(memory_order_seq_cst) have the semantics of a full memory barrier?
Can x86 reorder a narrow store with a wider load that fully contains it?
Does standard C++11 guarantee that memory_order_seq_cst prevents StoreLoad reordering of non-atomic around an atomic?
When are x86 LFENCE, SFENCE and MFENCE instructions required?