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Alex
Alex has asked
140
questions and find answers to
13
problems.
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1.0k
EtPoint
115
Vote count
140
questions
13
answers
About
Alex questions
How to use make_transform_iterator() with counting_iterator<> and execution_policy in Thrust?
What is the difference between "Interrupt coalescing" and the "Nagle algorithm"?
Do Cache, Store Buffer and BIU/WCB have separate physical buffers in CPU for each, or a single for all?
Can I use <stdatomic.h> from C11 in Linux driver, or do I must to use Linux functions of memory-barriers?
Can I use Quadro K4000 and K2000 for GPUDirect v2 Peer-to-peer (P2P) communictation?
How can I get a window position (x,y) created by using OpenCV?
Are there any benchmarks for CUDA-GPU or for MPI-CPU+CUDA-GPU? [closed]
What is the impact SFENCE and LFENCE to caches of neighboring cores?
Can I use a single address space for the GPU, CPU and FPGA look like to CUDA UVA?
How can I get the list of GPU cards to which are connected monitors?
Alex answers
How can I get the list of GPU cards to which are connected monitors?
should I label and train on all objects that exist in the training set (yolo darknet)
Concatenating template parameter packs for a unary argument
Does the semantics of `std::memory_order_acquire` requires processor instructions on x86/x86_64?
Does atomic_thread_fence(memory_order_seq_cst) have the semantics of a full memory barrier?
Can x86 reorder a narrow store with a wider load that fully contains it?
Does standard C++11 guarantee that memory_order_seq_cst prevents StoreLoad reordering of non-atomic around an atomic?
When are x86 LFENCE, SFENCE and MFENCE instructions required?
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