looking for a CRC implementation in Systemverilog

Question

All, I'm looking for a class or module that implements a CRC generator (or checker). I could create one from scratch, but if there's a ready made one out there that might be a real time saver :-)

Thanks! Ran

Answer 1

Here another example for the CRC calculation. The following examples calculate CRC sequentialy. Therefore, they are slower in comparison with the other solutions that calculate each CRC bit in parallel using XOR. However, I find this solution more "customizable" in case you need a different POLYNOM.

localparam CRC32POL = 32'hEDB88320; /* Ethernet CRC-32 Polynom, reverse Bits */

function automatic bit[31:0] genCRC32(input bit [7:0] databyte_stream[]);
    int unsigned i, j;
    bit [31:0] crc32_val = 32'hffffffff; // shiftregister,startvalue 
    bit [7:0]  data;

    //The result of the loop generate 32-Bit-mirrowed CRC
    for (i = 0; i < databyte_stream.size; i++)  // Byte-Stream
    begin
        data = databyte_stream[i];
        for (j=0; j < 8; j++) // Bitwise from LSB to MSB
        begin
            if ((crc32_val[0]) != (data[0])) begin
                crc32_val = (crc32_val >> 1) ^ CRC32POL;
            end else begin
                crc32_val >>= 1;
            end
            data >>= 1;
        end
    end
    crc32_val ^= 32'hffffffff; //invert results
    return crc32_val;
endfunction : genCRC32

You can have an automatic generation of your CRC from the following website http://www.easics.com/services/freesics/crctool.html

A similar implementation in C language using TOPBIT and not LSB bit. from the Altera examples: https://www.altera.com/content/dam/altera-www/global/en_US/others/support/examples/download/crc_accelerator.zip

In german, in the wikipedia. There are examples on how to calculate this. https://de.wikipedia.org/wiki/Zyklische_Redundanzprüfung

From: https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-crc-acceleration.html

An example in systemverilog of a fully configuragle CRC calculator would be

localparam CRC_BW        = 8;
localparam CRCXPOLYREV  = 'hE0;    /* CRC-8 Polynom, umgekehrte Bitfolge */
localparam CRCXPOLY     = 'h07;    /* CRC-8 Polynom,  Bitfolge */

function automatic logic[CRC_BW-1:0] generateCRC_X(
     logic [7:0] databyte_stream[],
     input logic reversed_poly=0,
     input logic[CRC_BW-1:0] start_crc_value='1, 
     input logic[CRC_BW-1:0] final_crc_xor_value='0,
     input logic do_end_crc_reversebits=0);
    int unsigned i, j;
    bit [CRC_BW-1:0] crcx_tmp,crcx_val = start_crc_value; /* Schieberegister, Startwert (111...) */
    bit [7:0]  data;


    //Ergebnis der Schleife gibt 8-Bit-gespiegelte CRC
    for (i = 0; i < databyte_stream.size; i++)  // Byte-Stream
    begin
        if (reversed_poly==1) begin
            data = databyte_stream[i];

            for (j=0; j < 8; j++) // from LSB to MSB in one byte!
            begin
                if ((crcx_val[0]) != (data[0]))
                    crcx_val = (crcx_val >> 1) ^ CRCXPOLYREV;
                else
                    crcx_val >>= 1;

                data >>= 1;
            end
        end else begin
            data = databyte_stream[i];
            for (j=0; j < 8; j++) // from LSB to MSB in one byte
            begin
                if ((crcx_val[CRC_BW-1]) != (data[7]))
                    crcx_val = (crcx_val << 1) ^ CRCXPOLY;
                else
                    crcx_val <<= 1;

                data <<= 1;
            end
        end
    end
    crcx_val ^= final_crc_xor_value; //Ergebnis invertieren
    if (do_end_crc_reversebits==1) begin
        for (j=0; j < CRC_BW; j++) // from LSB to MSB in the CRC bitwidth
        begin
            crcx_tmp[CRC_BW-1-j]=crcx_val[j];//reversed
        end
        crcx_val=crcx_tmp;
    end
    return crcx_val;
endfunction : generateCRC_X

To test the CRC i recommend http://www.zorc.breitbandkatze.de/crc.html