How to have config option in Makefile

Question

My main project directory has 4 sub-directories and each sub directory has some .c and .S files. I have written only one Makefile outside which contains lines like this:

...

AS_SRC= $(wildcard cpu/*.S) $(wildcard drivers/*.S) $(wildcard lib/*.S) $(wildcard init/*.S)
C_SRC= $(wildcard cpu/*.c) $(wildcard drivers/*.c) $(wildcard lib/*.c) $(wildcard init/*.c)

OBJS =  $(AS_SRC:.S=.o) $(C_SRC:.c=.o)

.PHONY: all
all: $(TARGET).bin

%.o: %.S
    @$(CC) -x assembler-with-cpp $(ASFLAGS) $< -o $@

%.o: %.c
    @$(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@

$(TARGET).elf: $(OBJS)
    @$(CC) $^ $(LFLAGS) -o $@

$(TARGET).bin: $(TARGET).elf
    @$(OC) -S -O binary $< $@

...

I understand that this is not a very good way to write Makefile. I want to have a .config file based on which It will be decided on what files to compile. Also I would like to use those config options in code something like #ifdef CONFIG_SOMETHING. I tried to understand from main Makefile of Linux kernel code and implement something similar, however that Makefile seems too complex.

Can anyone give suggestion on how to go about it? I already tried searching google but couldn't find any hint on how to go about having a config file.

Answer 1

If the config file follows the Makefile rules (var=value), you can use include

In your Makefile:

CONFIG = default.config
include ${CONFIG}

ifdef (... test on CONFIG setting)
endif

When make is invoked without parameters (that is make target), it will use the 'default' config file (default.config above). To run make with a different config use make CONFIG=alt.config ...