How to dynamically add IO ports to a Chisel Bundle?

Question

How can you dynamically add inputs or outputs to a Bundle in order to achieve the equivalent of this pseudocode.

class MyBundle extends Bundle {
  for( i <- 1 to 10) {
     val foo_<i> = UInt(i.W)
  }
}

Note that I would like to not only create 10 dynamic ports but would also like that the index value would be reflected in the port name and port size. I think MixedVec cast to Bundle can potentially offer something similar not quite what I am looking for.

Answer 1

One way to do it is use Record instead of Bundle. Here's a pointer to the chisel3 test of the Record construct RecordSpec.scala

As an example based on your pseudocode. It would look like this

  class MyBundle extends Record {
    val elements = ListMap(Seq.tabulate(10) { i =>
      s"foo_$i" -> UInt(i.W)
    }:_*)
    override def cloneType: this.type = (new MyBundle).asInstanceOf[this.type]
  }