How to add custom instruction to RISCV cross compiler?

Question

I cloned riscv-tools (https://github.com/riscv/riscv-tools) and riscv-gnu-toolchain ( https://github.com/riscv/riscv-gnu-toolchain) and was able to get Spike, pk, and the cross compiler (riscv64-unknown-elf-gcc) to work. I want to extend this and be able to add custom instructions and found this tutorial: https://nitish2112.github.io/post/adding-instruction-riscv/ but it's a bit outdated. The current RISCV GNU Toolchain repo does not have a riscv-binutils-gdb directory but does have a riscv-binutils directory and a riscv-gdb directory so I tried using the files in those directories instead when adding the instruction.

After I added the opcode to riscv-tools/riscv-opcodes/opcodes and to the files in riscv-gnu-toolchian/riscv-{binutils, gcb} and built it running the following:

sudo ./configure --prefix=/home/me/riscv64
sudo make newlib -j $(nproc)
sudo make linux -j $(nproc)
export PATH="$PATH:/home/me/riscv64/bin"
export RISCV="/home/me/riscv64"

I then tested it by running

riscv64-unknown-elf-gcc -o mod mod.c

with the same mod.c file in the tutorial except that I added a semicolon after asm inlining to get it to pass the compiler. I then get the following error from the assembler:

mod.c:7: Error: unrecognized opcode `mod a5,a5,a4'

Is there something that I am doing wrong? Thank you for your help and time.

Answer 1

It looks like that tutorial is indeed out of date. Fortunately, the RISC-V codebase has made it easier to add a new instruction. The instructions in https://github.com/riscv/riscv-isa-sim are pretty helpful:

Adding an instruction to the simulator requires two steps:

1. Describe the instruction's functional behavior in the file riscv/insns/.h. Examine other instructions in that directory as a starting point.

2. Add the opcode and opcode mask to riscv/opcodes.h. Alternatively, add it to the riscv-opcodes package, and it will do so for you:

   $ cd ../riscv-opcodes $ vi opcodes // add a line for the new instruction $ make install

3. Rebuild the simulator.

The riscv-opcodes repository is called on by the cross-compiler codechain, the assembler, as well as the simulator, so it should work to just rebuild those. To get it added to the cross compiler, and more importantly to have the cross compiler actually emit that instruction (in this case mod) is going to be many orders of magnitude more difficult, which is why the blog used inline assembly.