Communication between processor and high speed perihperal

Question

Considering that a processor runs at 100 MHz and the data is coming to the processor from an external device/peripheral at the rate of 1000 Mbit/s (8 Bits/Clockcycle @ 125 MHz), which is the best way to handle traffic that comes at a higher speed to the processor ?

Answer 1

First off, you can't do it in software. There would be no way to sample the digital lines at a sufficient rate, or to doing anything useful with it.

You need to use a hardware FIFO buffer or memory cell. When a data burst comes in, it can be buffered in the high speed FIFO and then read out as needed by the processor.

Drop in high speed FIFO chips are surprisingly expensive (though most are dual ported). To cut cost, you would be best off using an SRAM chip, and a hardware adder to increment the address lines on incoming data.