Avoid using inout in VHDL

Question

I want to avoid using inout at the following code.

Is there any way I can do it? For example a helping signal?

entity LA_Unit is
    Port ( Cin : in    STD_LOGIC;
           P   : in    STD_LOGIC_VECTOR (3 downto 0);
           G   : in    STD_LOGIC_VECTOR (3 downto 0);
           C3  : out   STD_LOGIC;
           C   : inout STD_LOGIC_VECTOR (2 downto 0));
end LA_Unit;

architecture Behavioral of LA_Unit is
begin
  C(0) <= (P(0) and Cin) xor G(0);
  C(1) <= (P(1) and C(0)) xor G(1);
  C(2) <= (P(2) and C(1)) xor G(2);
  C3   <= (P(3) and C(2)) xor G(3);
end Behavioral;

Answer 1

If the purpose is simply to provide the intermediate value of C as an output to the module, there are different options to avoid inout.

If the tools support VHDL-2008, you can simply change inout to out, and then the C can still be read internally.

If the tools only support VHDL-2002, then you can still change the inout to out, but you then need an internal signal like:

architecture Behavioral of LA_Unit is
  signal C_int : std_logic_vector(2 downto 0);
begin
  C_int(0) <= (P(0) and Cin) xor G(0);
  C_int(1) <= (P(1) and C_int(0)) xor G(1);
  C_int(2) <= (P(2) and C_int(1)) xor G(2);
  C3       <= (P(3) and C_int(2)) xor G(3);
  C        <= C_int;
end Behavioral;

As xvan also write, only use inout for toplevel ports on the chip, or for special test-bench use, since inout are not supported internally in a chip.